• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In the related art, as the semiconductor device becomes increasingly integrated, the critical dimension of the gate becomes smaller and the length of the channel formed under the gate oxide film becomes extremely short. There was a problem that the reliability is lowered. In view of the above problems, the present invention includes forming a well on an upper portion of a semiconductor substrate, and etching a portion of the well to a predetermined depth through a first photolithography process; After filling the first oxide layer in the etched region of the well, the upper portion of the well that is not primary etched through the secondary photolithography process is etched to the same depth as the primary photolithography process, and then the first oxide layer is removed. Forming an upper portion of the upper portion in an uneven shape; Forming a gate oxide film, a polysilicon, and a second oxide film sequentially on the wells of the uneven shape, and then forming a gate on the wells of the iron type through a third photolithography process; Fabricating a semiconductor device comprising implanting a low concentration of impurity ions onto the gate-formed semiconductor substrate, forming a gate sidewall, and injecting a high concentration of impurity ions to form an LED structure of low concentration and high concentration source / drain By increasing the length of the channel in the gate of the same critical dimension through the method, it is possible to suppress the short-channel effect due to high integration as possible to improve the reliability of the semiconductor device.
    公开号:KR19990074204A
    申请号:KR1019980007638
    申请日:1998-03-07
    公开日:1999-10-05
    发明作者:허익
    申请人:김영환；현대반도체 주식회사；
    IPC主号:
    专利说明:

    Manufacturing method of semiconductor device
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for preventing short channel effects caused by shortening of gate length due to high integration of the semiconductor device.
    Referring to the accompanying drawings, a conventional method for manufacturing a semiconductor device is as follows.
    1A through 1E are cross-sectional views showing a conventional method of manufacturing a semiconductor device. As shown in FIG. 1A to 1E, after forming a well 2 on a semiconductor substrate 1, a gate oxide film ( 3) forming (FIG. 1A); Sequentially depositing the doped polysilicon 4 and the cap oxide film 5 on the gate oxide film 3 (FIG. 1B); After applying photoresist PR1 on the oxide film 5, exposing and developing part thereof, the exposed oxide film 5, polysilicon 4 and gate oxide film 3 are sequentially etched to form a gate. (Step 1c); After removing the photoresist PR1 and injecting a low concentration of impurity ions onto the semiconductor substrate 1 using the gate as a mask to form a low concentration source / drain 6, an oxide film is formed on the upper surface of the semiconductor substrate 1. (7) forming (FIG. 1D); The oxide film 7 is selectively etched to form sidewalls 8 on the side of the gate, and then a high concentration of impurity ions are implanted onto the semiconductor substrate 1 using the gate and sidewalls 8 as masks. The drain 9 is formed (Fig. 1E). Hereinafter, a method of manufacturing a conventional semiconductor device as described above will be described in more detail.
    First, as shown in FIG. 1A, the well 2 is formed on the semiconductor substrate 1, and then the gate oxide film 3 is formed on the well 2. At this time, the well 2 is formed by oxidizing the surface of the semiconductor substrate 1, implanting impurity ions to prevent damage due to ion implantation, and diffusing them through a heat treatment process.
    As shown in FIG. 1B, the polysilicon 4 and the oxide film 5 are sequentially deposited on the gate oxide film 3.
    Then, as shown in FIG. 1C, after the photoresist PR1 is applied on the oxide film 5, a part of the light is exposed and developed, the exposed oxide film 5, the polysilicon 4, and the gate oxide film 3 are exposed. Are sequentially etched to form a gate. At this time, the formation of the gate using the photoresist PR1 is a conventional photolithography process, and the oxide film 5, the polysilicon 4, and the gate oxide film 3 deposited in the region except the gate region through the photoresist PR1. Are exposed, and they are sequentially etched to expose the wells 2.
    Then, as shown in Fig. 1D, the photoresist PR1 is removed, and a low concentration source / drain 6 is formed by implanting low concentration impurity ions onto the semiconductor substrate 1 using the gate as a mask. An oxide film 7 is formed on the entire upper surface of the substrate 1.
    Then, as shown in FIG. 1E, the oxide film 7 is selectively etched to form sidewalls 8 on the side surfaces of the gate, and then the gate and sidewalls 8 are masked on the semiconductor substrate 1 with high concentration. Impurity ions are implanted to form a high concentration source / drain 9.
    At this time, the reason for forming the low concentration and high concentration source / drain (6,9) through the side wall (8) is to form a lightly doped drain (LDD) structure to punch through (punch through) due to the influence of the short channel This is to suppress the occurrence as much as possible.
    However, in the conventional method of manufacturing a semiconductor device as described above, as the semiconductor device becomes more and more integrated, the critical dimension (CD) of the gate becomes smaller and the length of the channel formed under the gate oxide film becomes extremely short, thereby shortening the channel. There is a problem that the reliability of the semiconductor device is lowered by the effect.
    The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can increase the length of the channel without changing the threshold of the gate.
    1 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.
    Figure 2 is a cross-sectional view showing an embodiment of the present invention.
    *** Description of the symbols for the main parts of the drawings ***
    11: semiconductor substrate 12: well
    13,16,18 oxide film 14 gate oxide film
    15: polysilicon 17: low concentration source / drain
    19: side wall 20: high concentration source / drain
    An object of the present invention as described above is to form a well on the upper portion of the semiconductor substrate, and then etching a portion of the well to a predetermined depth through the first photolithography process; After filling the first oxide layer in the etched region of the well, the upper portion of the well that is not primary etched through the secondary photolithography process is etched to the same depth as the primary photolithography process, and then the first oxide layer is removed. Forming an upper portion of the upper portion in an uneven shape; Forming a gate oxide film, a polysilicon, and a second oxide film sequentially on the wells of the uneven shape, and then forming a gate on the wells of the iron type through a third photolithography process; It is achieved by injecting a low concentration of impurity ions onto the gate formed semiconductor substrate, forming a gate sidewall, and injecting a high concentration of impurity ions to form an LED structure of low concentration and high concentration source / drain. When described in detail with reference to the accompanying drawings, a method for manufacturing a semiconductor device according to the present invention.
    2A to 2J are cross-sectional views showing an embodiment of the present invention. As shown therein, a well 12 is formed on an upper portion of a semiconductor substrate 11 and a photoresist is formed on the well 12. After applying PR1), exposing and developing to expose a portion of well 12 (FIG. 2A); First etching a part of the exposed well 12 to a predetermined depth, and then removing the photoresist PR1 (FIG. 2B); Filling the oxide film 13 in the etched region of the well 12 (FIG. 2C); Applying photoresist PR2 on top of the oxide film 13 and the well 12, and then exposing and developing to expose the well 12 in the unetched region (FIG. 2D); Etching the exposed well 12 to the same depth as the primary etching, and then removing the photoresist PR2 to form an upper portion of the well 12 in an uneven shape (FIG. 2E); Removing the oxide film 13 filled in the primary etched region of the well 12 to expose the well 12 (FIG. 2F); Sequentially forming a gate oxide film 14, a polysilicon 15, and an oxide film 16 on the well 12 (Fig. 2G); After photoresist PR3 is applied on the oxide film 16, it is exposed and developed to define an iron-shaped region on the well 12, and the exposed oxide film 16 and polysilicon 15 are defined. And etching the gate oxide film 14 to form a gate (FIG. 2H); The photoresist PR3 is removed and a low concentration source / drain 17 is formed by implanting low concentration impurity ions onto the semiconductor substrate 11 using the gate as a mask, and then an oxide film is formed on the upper surface of the semiconductor substrate 11. Forming 18 (FIG. 2I); The oxide film 18 is selectively etched to form sidewalls 19 on the side of the gate, and then a high concentration of impurity ions are implanted onto the semiconductor substrate 11 using the gate and sidewalls 19 as masks. Forming a drain 20 (FIG. 2J). Hereinafter, an embodiment of the present invention as described above will be described in more detail.
    First, as shown in FIG. 2A, the well 12 is formed on the semiconductor substrate 11, the photoresist PR1 is applied on the well 12, and then exposed and developed to expose the well 12. Part of the At this time, the well 12 is formed by oxidizing the surface of the semiconductor substrate 11 as in the prior art, implanting impurity ions, and diffusing them through a heat treatment process.
    As shown in FIG. 2B, a part of the exposed well 12 is first etched to a predetermined depth, and then the photoresist PR1 is removed.
    As shown in FIG. 2C, the oxide film 13 is filled in the etched region of the well 12. At this time, the oxide film 13 is deposited on the upper front surface of the well 12 and then etched back for planarization.
    As shown in FIG. 2D, the photoresist PR2 is coated on the oxide film 13 and the wells 12, and then exposed and developed to expose the wells 12 in the unetched region.
    As shown in FIG. 2E, the exposed well 12 is secondly etched to the same depth as the first etching, and then the photoresist PR2 is removed to form an upper portion of the well 12 in an uneven form. At this time, the upper portion of the well 12 is formed in the form of iron on the boundary between the primary etched region and the secondary etched region.
    Then, as shown in FIG. 2F, after the photoresist PR3 is applied on the oxide film 16, the photoresist PR3 is exposed and developed to define an iron-shaped region on the well 12, and the exposed oxide film ( 16), the polysilicon 15 and the gate oxide film 14 are etched to form a gate.
    Thereafter, the process for forming the LED structure shown in Figs. 2G to 2J is the same as that shown in Figs. 1D and 1E, and thus will be omitted.
    The method of manufacturing a semiconductor device according to the present invention as described above has the effect of increasing the length of the channel in the gate of the same critical dimension, thereby improving the reliability of the semiconductor device by suppressing the short channel effect due to the high integration.
    权利要求:
    Claims (1)
    [1" claim-type="Currently amended] Forming a well on an upper portion of the semiconductor substrate, and etching a portion of the well to a predetermined depth through a primary photolithography process; After filling the first oxide layer in the etched region of the well, the upper portion of the well that is not primary etched through the secondary photolithography process is etched to the same depth as the primary photolithography process, and then the first oxide layer is removed. Forming an upper portion of the upper portion in an uneven shape; Forming a gate oxide film, a polysilicon, and a second oxide film sequentially on the wells of the uneven shape, and then forming a gate on the wells of the iron type through a third photolithography process; Injecting a low concentration of impurity ions onto the gate formed semiconductor substrate, forming a gate sidewall, and injecting a high concentration of impurity ions to form an LED structure of a low concentration and a high concentration source / drain. Method of manufacturing a semiconductor device.
    类似技术:
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    同族专利:
    公开号 | 公开日
    KR100259362B1|2000-06-15|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-03-07|Application filed by 김영환, 현대반도체 주식회사
    1998-03-07|Priority to KR1019980007638A
    1999-10-05|Publication of KR19990074204A
    2000-06-15|Application granted
    2000-06-15|Publication of KR100259362B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019980007638A|KR100259362B1|1998-03-07|1998-03-07|Method for manufacturing semiconductor device|
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